| @@ -89,12 +89,25 @@ static int get_flat_ccs_offset(struct xe_gt gt, u64 tile_size, u64 poffset) |
| 89 | 89 | offset = offset_hi << 32; / HW view bits 39:32 / |
| 90 | 90 | offset |= offset_lo << 6; / HW view bits 31:6 / |
| 91 | 91 | offset = num_enabled; / convert to SW view / |
| 92 | | - offset = round_up(offset, SZ_128K); / SW must round up to nearest 128K / |
| 93 | 92 |
|
| 94 | | - / We don't expect any holes / |
| 95 | | - xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(>_to_tile(gt)->mmio, GSMBASE) - |
| 96 | | - ccs_size), |
| 97 | | - "Hole between CCS and GSM.\n"); |
| | 93 | + / |
| | 94 | + * Everything below this offset is handed to the VRAM |
| | 95 | + * allocator, so it has to be the first address the |
| | 96 | + * compression hardware owns, rounded down. Rounding it up |
| | 97 | + * publishes CCS storage as free memory. |
| | 98 | + / |
| | 99 | + offset = round_down(offset, SZ_4K); |
| | 100 | + |
| | 101 | + / |
| | 102 | + * CCS storage must not run into GSM. The old check compared |
| | 103 | + * the offset against GSMBASE - ccs_size for equality, which |
| | 104 | + * could not fail: that value is 128K aligned, so it agreed |
| | 105 | + * with the rounded-up offset even when the base was not 128K |
| | 106 | + * aligned - exactly the case this fixes. |
| | 107 | + */ |
| | 108 | + xe_assert_msg(xe, offset + ccs_size <= |
| | 109 | + xe_mmio_read64_2x32(>_to_tile(gt)->mmio, GSMBASE), |
| | 110 | + "CCS overlaps GSM.\n"); |
| 98 | 111 | } else { |
| 99 | 112 | reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR); |
| 100 | 113 | offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K; |
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